CV

Visiting PhD Student

ISEC, TU Graz

Three-month research visit, March to June 2026. Collaborated with Daniel Gruss’s group on side-channel attacks on SoC devices.

Doctoral Researcher

Université de Rennes / IRISA / INRIA -SUSHI Team (CentraleSupélec)

Research on the security of heterogeneous SoC-FPGA platforms for cloud and edge computing.

• Focusing on leakage risks from shared hardware resources and multi-tenant execution.
• Study of microarchitectural behavior through embedded power sensing rather than traditional timing analysis.
• Development of MIRABELLE, a framework combining on-chip sensing and signal processing to identify leakage sources invisible to software-only observation.

Detection Engineer

Ministère des Armées

• Designed graph-based models (Tid2Vec) to represent MITRE ATT&CK techniques and infer semantic relationships.
• Built an unsupervised Transformer-based pipeline for event-log analysis, including noise reduction and automatic pattern extraction.

Detection Engineering Intern

Apple Inc.

• Optimized large-scale security telemetry with Databricks and Apache Spark, reducing false positives in detection workflows.

Security Engineering Intern

Ministère des Armées

• Designed and deployed a multi-antivirus sandbox platform for malware detection and behavioral analysis.

Ph.D.

Université de Rennes / IRISA / INRIA / SUSHI Team (CentraleSupélec)

Hardware Security

• Supervisors: Lilian Bossuet, Rubén Salvador, Maria Méndez Real, Alessandro Palumbo, Thomas Rokicki.
• PROACT Training School (Crete, June 2025): hardware security, side-channel analysis, embedded cryptography.
• MICSEC International Winter School on Microarchitectural Security (Télécom Paris, December 2025).

Diplôme d'Ingénieur

IMT Atlantique

Telecommunications, Networks, and Computer Engineering

• Research program: advanced musical source separation (segmentation models, Transformer ViT autoencoders).
• Project: modular FPGA synthesizer for frequency-domain processing and real-time sound synthesis.

Bachelor's Degree

Université de Rennes -IUT de Saint-Malo

Networks and Telecommunications

HOMARD: Hammering Off-chip Memory via Aggregate power Rail Disclosure

IEEE Symposium on Security and Privacy (S&P), 2027. Accepted, to appear.

Eliott Quéré, Li-Chung Chiang, Carina Fiedler, Thomas Rokicki, Maria Méndez Real, Alessandro Palumbo, Lilian Bossuet, Rubén Salvador, and Daniel Gruss. Project page · Code.

SnoopyPower! Remote Power Attacks on Cache and Coherence Paths

IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2026.

Eliott Quéré, Maria Méndez Real, Alessandro Palumbo, Thomas Rokicki, Lilian Bossuet, and Rubén Salvador.

Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments

Rendez-Vous de la Recherche et de l'Enseignement de la Sécurité des Systèmes d'Information (RESSI), 2025.

Eliott Quéré, Maria Méndez Real, Alessandro Palumbo, Lilian Bossuet, and Rubén Salvador.